Electrostatic discharge (ESD) may cause damage to semiconductor devices on an integrated circuit during handling of the integrated circuit chip package. Prevention of such damage generally is provided by protection circuits incorporated into the chip of the integrated circuit. In general, such protection circuits include a switch which is capable of conducting relatively large currents during an ESD event. Various devices such as a Silicon Controlled Rectifier (SCR) have been utilized to provide the switching function required to essentially shunt the protected circuitry during an ESD event. Previous circuits and structures used for ESD protection can withstand high levels of ESD stress. However, recent advances in technology have produced devices which can fail at voltage levels lower than the triggering voltages of some prior art protection circuits.
One protection device having a lower trigger voltage is shown in FIG. 1. This device is known as a LVTSCR (low voltage threshold SCR) and includes a lateral SCR that incorporates a trigger nMOS transistor. The protection device is a gated SCR structure 10 having a polysilicon gate 12 connected to ground. SCR structure 10 comprises an anode 14 connected to p+ region 16 and n+ region 18 both of which are located in an n-well 20. The cathode 22 of SCR structure 10 is an n+ region 24 connected to ground and polysilicon gate 12. The trigger nMOS comprises two n+ regions 24 and 28 (i.e., the source/drain regions) separated by gate 12. N+ region 24 is also the cathode of the SCR and both n+ region 24 and gate 12 are connected to ground. In operation, the parasitic bipolar transistor 26 associated with gate 12 (of the trigger nMOS) will begin to conduct current at a lower voltage level than the triggering voltage of a typical SCR. The current conducted through parasitic bipolar transistor 26 triggers SCR structure 10, which, in turn, dissipates the ESD event. Polysilicon gate 12 connected to ground thus reduces the triggering voltage of a typical SCR structure from about 50 volts to about 10-15 volts in a 0.5 micron CMOS process.
The protection device of FIG. 1, however, uses field oxide or LOCOS isolation 21 between active areas. Currently, LOCOS isolation is being replaced with shallow trench isolation. Shallow trench isolation (STI) can require less surface area and thus allow for tighter densities on an integrated circuit. Unfortunately, when the LOCOS isolation of the device of FIG. 1 is replaced with shallow trench isolation, which extends deeper into the substrate surface, the holding voltage and trigger current of the lateral SCR both increase. This is due to the fact that the trench isolation interferes with the surface conduction of the lateral SCR. This can result in the trigger nMOS portion of the device of FIG. 1 failing before the lateral SCR is fully on or a high on-resistance for the SCR. The ESD failure threshold of the LVTSCR with trench isolation is approximately 1000 V for a 50 micron wide device compared to greater than 3000 V for a LOCOS isolated device.